In the field of high speed performance logic circuits, there is current development and research for large-capacity capacitors. For large-capacity capacitors having a polysilicon/insulator/polysilicon (PIP) structure, since conductive polysilicon is used for upper and lower electrodes, oxidation occurs at an interface between the upper electrode and a dielectric layer and also at an interface between the lower electric and the dielectric layer. A native oxide is formed as a result of the oxidation, thereby causing a problem of reduction in the overall size of the capacitance. To solve such a problem, a metal/insulator/metal (MIM) structure has been applied to the capacitor. The MIM structure capacitor is generally employed by high-quality semiconductor devices requiring a high Q-value since the MIM structure capacitor does not have a parasitic capacitance therein formed by depletion. In addition, by employing a stack structure of the capacitor from a single layer to multiple layers, the large-capacity capacitance can be guaranteed.
As illustrated in example FIG. 1, a stack MIM capacitor may be structured in a manner that a first capacitor and a second capacitor are deposited on and/or over a semiconductor substrate. The first capacitor may have a laminated structure including first lower electrode 110 as a metal layer on and/or over semiconductor substrate 100, first dielectric layer 121 as a dielectric layer formed on and/or over first lower electrode 110, and first upper electrode 122 as a metal layer formed on and/or over first dielectric layer 121. The second capacitor may include second lower electrode 123 as a metal layer formed on and/or over first upper electrode 122, second dielectric layer 130 as a dielectric layer formed on and/or over second lower electrode 123, and second upper electrode 140 as a metal layer formed on and/or over second dielectric layer 130.
Because first upper electrode 122 of the first capacitor is formed on and/or over a smaller area than first lower electrode 110, areas of those two electrodes do not correspond to each other. Therefore, when the electrodes of the first capacitor have different surface areas, the number of fabrication processes is increased in order to fabricate and apply different masks. Furthermore, since the second capacitor also includes two electrodes having different surface areas, the number of processes is further increased in comparison with in a single-layer capacitor, thereby deteriorating the fabrication efficiency. Also, the capacitance may be deteriorated.